Recently, an in-vehicle equipment or an industrial robot become highly functionally. A system performs to drive an actuator and to operate an air bag device based on an output corresponding to calculation result of data such as an image, a sound and an acceleration obtained from signals of various sensors. A semiconductor device is used for the system, and formed of one chip device. The device includes many kinds of electric elements, which are separated from each other with junction isolation and/or oxide film isolation. The device is defined as a composite device, which is disclosed in, for example, JP-A-H08-181211.
An element isolation structure for providing the composite device is the junction isolation structure or the oxide film isolation structure. In the junction isolation structure, a PN junction surrounds an element so that the element is isolated. In the oxide film isolation structure, an oxide film is formed in a trench, which is formed on a SOI layer of a SOI substrate and reaches an embedded oxide film, so that an element is isolated with the oxide film. The oxide film isolation structure has surge resistance higher than the junction isolation structure since the oxide film isolation structure has no parasitic element. Further, the dimensions of the oxide film isolation structure are smaller than those of the junction isolation structure.
However, since the composite device includes various circuits, it is necessary to thicken the thickness of the SOI layer. For example, when a logic circuit and a high power circuit are formed in the same substrate, it is necessary to increase the thickness of the SOI layer for securing a breakdown voltage of the high power circuit. Here, the logic circuit includes a CMOS for performing calculation, and the high power circuit includes a diode for protecting from ESD (i.e., electro static discharge) and a LDMOS for handling high power, i.e., high voltage electricity. Accordingly, in the logic circuit, a well layer is formed in the thick SOI layer, and an element is formed in the well layer. Thus, a parasitic capacitor is formed at a boundary of the well layer, and the parasitic capacitance is not sufficiently small. The energy consumption increases, and calculation speed decreases.
Thus, it is required for a composite device to be formed of one chip device, and to reduce the thickness of the SOI layer even when the composite device includes a signal processor and a high power circuit.